The present invention relates to nonvolatile semiconductor memories.
A NAND type of flash EEPROM having such a memory cell array as shown in FIG. 1 has been hitherto known as one of nonvolatile semiconductor memories.
The memory cell array of the NAND flash EEPROM is composed of a number of NAND cell units. Each of the NAND cell units has a NAND series of memory cells (e.g., 16 memory cells), a source-side select gate transistor connected between one end of the NAND series of memory cells and a source line, and a drain-side select gate transistor connected between the other end of the NAND string and a bit line BLi.
The memory cell array is composed of a plurality of blocks BLkj. Control gate electrodes (word lines) CG0 to CG15, source-side select gate electrodes SGS, and drain-side select gate electrodes SGD extend in the row direction, while bit lines BLi extend in the column direction. A plurality of memory cells M0 to Mi connected to one word line forms a unit called PAGE.
Usually a page of data is read out in a single read operation. The read page of data is latched by a latch circuit and then output serially to the outside of the memory chip.
For such a NAND flash EEPROM it is important to obtain a large storage capacity and reduce the area of the memory cell array for small chip sizes. To this end, it is required to reduce the size of memory cells and the spacing between two adjacent select gate lines (electrodes).
Usually the select gate line is provided with contact areas, which are large in area and prevent the spacing between two adjacent select gate lines from being reduced. When, in patterning the contact areas, misalignment occurs between the select gate line and the contact area due to resist misalignment, the resistance of the select gate line increases.
To the contact areas of the select gate line is connected a select gate bypass line, which is formed on an interlayer insulator on the word line (control gate line). In this case, in a read operation, capacitive coupling between the select gate bypass line and the word line may cause the potential on the selected word line in a selected block to rise in error.
It is an object of the present invention to reduce the spacing between two adjacent select gate lines (electrodes) independently of the size of contact areas and prevent the resistance of the select gate lines from increasing even if misalignment occurs between a select gate line and its associated contact areas in patterning the contact areas.
It is the other object of the present invention to prevent the potential on the selected word line in a selected block from varying in a read operation by devising a novel layout for select gate bypass lines on an interlayer insulator on word lines.
A nonvolatile semiconductor memory of the present invention has first and second select gate electrodes formed above the surface of a semiconductor substrate to be adjacent to each other in the column direction and extend in the row direction and a diffused layer formed in a region of the semiconductor substrate between regions of the semiconductor substrate that are located below the first and second select gate electrodes. Each of the first ad second select gate electrodes is composed of a first conductive layer and a second conductive layer located above the first conductive layer. The first conductive layer of the first select gate electrode has a plurality of first contact areas therefor, and the second conductive layer of the first select gate electrode has its portions removed that are located over the first contact areas. The first conductive layer of the second select gate electrode has a plurality of second contact areas therefor, and the second conductive layer of the second select gate electrode has its portions removed that are located over the second contact areas. The first contact areas and the second contact areas are located so that they are not opposed to each other. The second select gate electrode has its first and second conductive layers removed in portions that are opposed to the first contact areas, and the first select gate electrode has its first and second conductive layers removed in portions that are opposed to the second contact areas.
A nonvolatile semiconductor memory of the present invention has first and second select gate electrodes formed above the surface of a semiconductor substrate to be adjacent to each other in the column direction and extend in the row direction and a diffused layer formed in a region of the semiconductor substrate between regions of the semiconductor substrate that are located below the first and second select gate electrodes. Each of the first and second select gate electrodes is composed of a first conductive layer and a second conductive layer located above the first conductive layer. The first conductive layer of the first select gate electrode has a plurality of contact areas therefor and the second conductive layer of the first select gate electrode has its portions disconnected that are located above the contact areas so that the contact areas are exposed. The length in the column direction of each of the contact areas is larger than the gate electrode of the first select gate electrode. The length in the column direction of portions of the second conductive layer of the first select gate electrode that are in contact with the contact areas is larger than the gate length of the first select gate electrode.
The second conductive layer of the first select gate electrode has a pattern such that it bends in the column direction in its portions that are in contact with the contact areas of the first conductive layer.
A nonvolatile semiconductor memory of the present invention has first and second select gate electrodes formed above the surface of a semiconductor substrate to be adjacent to each other in the column direction and extend in the row direction and a diffused layer formed in a region of the semiconductor substrate between regions of the semiconductor substrate that are located below the first and second select gate electrodes. Each of the first ad second select gate electrodes is composed of a first conductive layer and a second conductive layer located above the first conductive layer. The first conductive layer of the first select gate electrode has a plurality of first contact areas therefor, and the second conductive layer of the first select gate electrode has its portions disconnected that are located above the first contact areas so that the first contact areas are exposed. The first conductive layer of the second select gate electrode has a plurality of contact areas therefor, and the second conductive layer of the second select gate electrode has its portions disconnected that are located above the second contact areas so that the second contact areas are exposed. The first contact areas and the second contact areas are located so that they are not opposed to each other.
A non-volatile semiconductor memory of the present invention comprises: a cell unit composed of a memory cell and a select gate transistor; and a select gate bypass line which is connected to the select gate line of the select gate transistor in the cell unit, and which is formed at an upper level of the select gate line. The select gate bypass line is located in an area other than right above the control gate line of the memory cell in the cell unit.
A non-volatile semiconductor memory of the present invention comprises: a first cell unit, which is located in a first block, and which is composed of a plurality of memory cells serially or in parallel connected therebetween and a select gate transistor which is connected to the plurality of memory cells; a second cell unit, which is located in a second block adjacent to the first block, and which is composed of a plurality of memory cells serially or in parallel connected therebetween and a select gate transistor which is connected to the plurality of memory cells; and a first select gate bypass line which is connected to the select gate line of the select gate transistor in the first cell unit, and which is formed at an upper level of the select gate line. The first select gate bypass line is located in an area other than right above a control gate line of the plurality of memory cells in the first cell unit.
A non-volatile semiconductor memory of the present invention comprises: a cell unit composed of a plurality of memory cells which are serially or in parallel connected therebetween, and first and second select gate transistors which are respectively connected to both ends of the plurality of memory cells; a select gate bypass line, which is connected to the select gate line of the first select gate transistor in the cell unit, and which not only is formed at an upper level of the select gate line, but located in an area other than right above a control gate line of the plurality of memory cells in the cell unit; and a circuit whereby in a data read operation, the select gate line of the first select gate transistor in the cell unit is charged after the select gate line of the second select gate transistor in the cell unit is charged.
A non-volatile semiconductor memory of the present invention comprises: a memory cell array composed of a plurality of memory cells located in a matrix; a word line extending in the row direction on the memory cell array; a bit line extending in the column direction on the memory cell array; a shunt area which is located in the memory cell and extends in the column direction, and where arrangement of any of the plurality of memory cells is forbidden; a first interconnection, which is located in the shunt area, and which applies a potential to an area where the plurality of memory cells are formed; and a second interconnection, which is located at an upper level of the first interconnection in the shunt area, and which is connected to the plurality of memory cells.
A non-volatile semiconductor memory of the present invention comprises: a memory cell array including a cell unit composed of a memory cell and a select gate transistor; a word line which is connected to the memory cell and extends in the row direction on the memory cell array; a select gate line which is connected to the select gate transistor and extends in the row direction on the memory cell array; a select gate bypass line which is formed at an upper level of the select gate line and extends in the the direction on the memory cell array; a shunt area which is located in the memory cell array and extends in the column direction, and where arrangement of any of memory cells is forbidden; a contact area, which is located in the shunt area, for connecting the select gate bypass line to the select gate line; a first interconnection, which is located in the shunt area, and which applies a potential to an area where the memory cell is formed; and a second interconnection which is located at an upper level of the first interconnection in the shunt area, and which is connected to the memory cell.
A non-volatile semiconductor memory of the present invention comprises: a memory cell array including a cell unit composed of a memory cell and a select gate transistor; a word line which is connected to the memory cell and extends in the row direction on the memory cell array; a select gate line which is connected to the select gate transistor and extends in the row direction on the memory cell array; a select gate bypass line which is formed at an upper level of the select gate line and extends in the row direction on the memory cell array; a plurality of shunt areas, which are located in the memory cell array and extends in the column direction, and where arrangement of any memory cell is forbidden; a first contact section for connecting the select gate bypass line to the select gate line; and a second contact section for applying a potential to an area where the memory cell is formed. The first and second contact sections are alternatively located in the plurality of shunt areas.
A non-volatile semiconductor memory of the present invention comprises: a memory cell array including first and second cell units, which are respectively located in blocks different from each other, and each of which composed of a memory cell and a select gate transistor; a first select gate line connected to the select gate transistor in the first cell unit; a second select gate line connected to the select gate transistor in the second cell unit; a select gate bypass line which is formed at an upper level of the first and second select gate lines; a shunt area, which is located in the memory cell array, and where arrangement of any of memory cells is forbidden; and a contact section, which is located in the shunt area, for connecting the select gate bypass line to the first select gate line. The second select gate line is disconnected in the shunt area where the contact area is located.
A non-volatile semiconductor memory of the present invention comprises: a memory cell array including a cell unit composed of a memory cell and a select gate transistor; a select gate bypass line which is formed at an upper level of the select gate line of the select gate transistor; first and second shunt areas, which are located in the memory cell array, and in either of which arrangement of any of memory cells is forbidden; a first contact section which is located in the first shunt area for connecting the select gate bypass line to the select gate line; and a second contact section, which is located in the second shunt area, for applying a potential to an area where the memory cell is formed. The select gate line is disconnected in the second shunt area where the second contact section is located.
A non-volatile semiconductor memory of the present invention comprises: a BLOCK block including a cell unit composed of a plurality of memory cells which are serially or in parallel connected therebetween and a select gate transistor connected to the plurality of memory cells; a first row decoder, which is located on one end side of the block, for producing a block select signal showing whether or not the BLOCK block is selected; and a second row decoder, which is located on the other end side of the block, for receiving the block select signal. The number of control gate lines of memory cells which are connected to the first row decoder in the cell unit is smaller than that of control gate lines of memory cells which are connected to the second row decoder in the cell unit.
A non-volatile semiconductor memory of the present invention comprises: a BLOCK block including a cell unit composed of n memory cells which are serially or in parallel connected therebetween and a select gate transistor connected to the n memory cells; a first row decoder, which is located on one end side of the block, for producing a block select signal showing whether or not the BLOCK block is selected; and a second row decoder, which is located on the other end side of the block, for receiving the block select signal. The first row decoder is connected to the select gate line of the select gate transistor in the cell unit and the control gate lines of j memory cells in the cell unit and the second row decoder is connected to the control gate lines of k (k greater than j, j+k=n) memory cells in the cell unit.
A non-volatile semiconductor memory of the present invention comprises: a memory cell array composed of a plurality of memory cells. A non-volatile semiconductor memory of the present invention comprises: a first isolation region which is constructed of a device isolation insulating layer of a STI structure and regularly located at virtually constant widths and pitches in the memory cell array; an active region which is isolated by the first isolation region and in which a plurality of memory cells are located; and a second isolation region which is constructed of a device isolation insulating layer of a STI structure and regularly located at larger widths and pitches than those of the first isolation insulating layer in the memory cell array.
A non-volatile semiconductor memory of the present invention comprises: a memory cell array composed of a plurality of memory cells. A non-volatile semiconductor memory of the present invention comprises: a device isolation region which is constructed of a device isolation insulating layer of a STI structure and regularly located at virtually constant widths and pitches in the memory cell array; an active region which is isolated by the isolation region and in which a plurality of memory cells are located; and a shunt area s which is located in the memory cell array, and in which arrangement of a memory cell is forbidden. The shunt area s is constructed of a device isolation insulating layer of a STI structure and regularly located in the memory cell array at larger widths and pitches than those of the isolation region.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.